This article explains how to compile a sample program, led, which is included in sythesijer_samples on DE0-Nano/Synthesijer. This shows how to write the build image, and execute it on DE0-Nano.

This article basically uses the same sample program as the article of DE0-Nano/Synthesijer_QuickStart, and the sample program makes an LDE on DE0-Nano blink.

In the led directory there is the make file. Then, build the file with make command.

$ cd ~/synthesijer_samples/sample/led/
$ make
java -cp /home/beat/synthesijer-20140818.jar synthesijer.Main
Output VHDL: counter.vhd
Output VHDL: led.vhd
Output Verilog HDL: counter.v
Output Verilog HDL: led.v
javac -cp /home/beat/synthesijer-20140818.jar:.
java -cp /home/beat/synthesijer-20140818.jar:. led_top

Create a project file on DE0-Nano System Builder. To be consist with the name of Synthesijer's sample, the name of the project file is led.

Move the created project file to Ubuntu. Change the name of led_top.v to something else.
On Ubuntu, edit led_top.qsf for matching led_top.vhd. led_top.vhd is a part of led, which has been built.

As exstick.ucf is defined, the pin-allocation is not specified for reset. Also, led is built, there are led_top.vhd, led.vhd, and counter.vhd are created. Copy these three files and placed them in the same directory.

$ vi exstick.ucf

NET reset      LOC = A12  | IOSTANDARD = LVCMOS33;    # "USER_RESET"
NET reset      TIG;

NET clk        LOC = N7 | IOSTANDARD = LVCMOS33;               # "USER_CLOCK"

NET clk TNM_NET = clk;
TIMESPEC ts_clk = PERIOD clk 25000 kHz;


$ vi led_top.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity led_top is
  port (
     clk : in std_logic;
     reset : in std_logic;
     q : out std_logic
end led_top;

$ vi led_top.qsf
set_location_assignment PIN_R8 -to clk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk
# set_location_assignment PIN_R8 -to CLOCK_50
# set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
set_location_assignment PIN_A15 -to q
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to q
#set_location_assignment PIN_A15 -to LED[0]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
# End of pin assignments by Terasic System Builder^M
set_global_assignment -name VHDL_FILE led.vhd^M
set_global_assignment -name VHDL_FILE counter.vhd^M
set_global_assignment -name VHDL_FILE led_top.vhd^M
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"^M

Then, the rest of steps is identical to what describes in DE0-Nano/Synthesijer_QuickStart.

Start up Quartus, and select Top.qpf from Open Project in the File, which is located at the menu bar.

$ quartus

  • Error message 1
    Click Start Complication in Processing at the menu bar.
    Start compiling the files, which are created in the project file.

    Caution: A lot of Warning will appear. But, there are no issues here. Please ignore it.

Click Pin Planner in Assignments section. Then, make sure that all changes (editing the file and relocating files) shown above are effective.

  • Error message 2
    Click Programmer in Tools section at the menu bar. Programmer works as writing (programming) a created image to DE0-Nano. Programmer also selects a device for being written. In this article, USB-Blaster is selected.

    If the screen indicates No Hardware, click Hardware Setting and select USB-Blaster, which can be found in “Currently selected hardware.” Please look at the screen shot below for the reference.

    Caution: If the choice of USB-Blaster is not be displayed, please check the rule file of udev.

As all process has been completed. Click Start, which is located in Programmer. Then, the created image is transferred to DE0-Nano.
As progress reaches at 100% (successful), LED0 on DE0-Nano starts blinking.


This is the end of operation check on quickstart.

Revision History

  • 2014/12/25 This article is initially uploaded

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Last-modified: 2014-12-25 (Thu) 06:54:51 (2700d)