DE0-Nano/Synthesijer_QuickStart
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[[labs.beatcraft.com]]~
[[DE0-Nano]]~
[[Synthesijer]]~
[[DE0-Nano/Synthesijer]]~
#Contents
* QuickStart [#abd7f553]
>
This article shows how to build a sample application, qui...
** synthesijer_samples/quickstart [#ua355892]
>
quickstart is a smple program, which enables to blink LED...
Build this sample program as it follows the directions, w...
$ cd ~/synthesijer_samples/sample/quickstart/
$ java -cp $SYNTHESIJER synthesijer.Main Test.java Top.j...
Output VHDL: Top.vhd
Output VHDL: Test.vhd
Output Verilog HDL: Top.v
Output Verilog HDL: Test.v
~
The next step is to create its project file with DE0-Nano...
#ref(SystemBuilder.png,,60%); ~
~
Transfer the created project to Ubuntu. Rename Top.v, whi...
~
Edit Top.qsf as it is shown below. This is due to Top.qsf...
$ vi Top.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Top is
port (
clk : in std_logic;
reset : in std_logic;
flag_return : out std_logic
);
end Top;
...<Skip>
~
$ vi Top.qsf
...<Skip>
#=======================================================...
# CLOCK
#=======================================================...
set_location_assignment PIN_R8 -to clk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" ...
#set_location_assignment PIN_R8 -to CLOCK_50
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL"...
#=======================================================...
# LED
#=======================================================...
set_location_assignment PIN_A15 -to flag_return
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" ...
#set_location_assignment PIN_A15 -to LED[0]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL"...
...<略>
#=======================================================...
# End of pin assignments by Terasic System Builder
#=======================================================...
set_location_assignment PIN_A11 -to reset
set_instance_assignment -name IO_STANDARD 2.5V -to reset
set_global_assignment -name VHDL_FILE Test.vhd
set_global_assignment -name VHDL_FILE Top.vhd
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "...
~
Start up Quartus, and select Top.qpf from Open Project in...
$ quartus
~
- Error message 1~
Click Start Complication in Processing at the menu bar.~
Start compiling the files, which are created in the proje...
~
''Caution'': A lot of Warning will appear. But, there are...
>
Click Pin Planner in Assignments section. Then, make sure...
~
- Error message 2~
Click Programmer in Tools section at the menu bar. Progra...
~
If the screen indicates No Hardware, click Hardware Setti...
~
''Caution'': If the choice of USB-Blaster is not be displ...
>
As all process has been completed. Click Start, which is ...
As progress reaches at 100% (successful), LED0 on DE0-Nan...
~
#ref(quartus003.png,,60%);~
~
#ref(quickstart.JPG,,20%);~
This is the end of operation check on quickstart.~
* Revision History [#j745fcc1]
>
- 2014/12/25 This article is initially uploaded~
End:
[[labs.beatcraft.com]]~
[[DE0-Nano]]~
[[Synthesijer]]~
[[DE0-Nano/Synthesijer]]~
#Contents
* QuickStart [#abd7f553]
>
This article shows how to build a sample application, qui...
** synthesijer_samples/quickstart [#ua355892]
>
quickstart is a smple program, which enables to blink LED...
Build this sample program as it follows the directions, w...
$ cd ~/synthesijer_samples/sample/quickstart/
$ java -cp $SYNTHESIJER synthesijer.Main Test.java Top.j...
Output VHDL: Top.vhd
Output VHDL: Test.vhd
Output Verilog HDL: Top.v
Output Verilog HDL: Test.v
~
The next step is to create its project file with DE0-Nano...
#ref(SystemBuilder.png,,60%); ~
~
Transfer the created project to Ubuntu. Rename Top.v, whi...
~
Edit Top.qsf as it is shown below. This is due to Top.qsf...
$ vi Top.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity Top is
port (
clk : in std_logic;
reset : in std_logic;
flag_return : out std_logic
);
end Top;
...<Skip>
~
$ vi Top.qsf
...<Skip>
#=======================================================...
# CLOCK
#=======================================================...
set_location_assignment PIN_R8 -to clk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" ...
#set_location_assignment PIN_R8 -to CLOCK_50
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL"...
#=======================================================...
# LED
#=======================================================...
set_location_assignment PIN_A15 -to flag_return
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" ...
#set_location_assignment PIN_A15 -to LED[0]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL"...
...<略>
#=======================================================...
# End of pin assignments by Terasic System Builder
#=======================================================...
set_location_assignment PIN_A11 -to reset
set_instance_assignment -name IO_STANDARD 2.5V -to reset
set_global_assignment -name VHDL_FILE Test.vhd
set_global_assignment -name VHDL_FILE Top.vhd
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "...
~
Start up Quartus, and select Top.qpf from Open Project in...
$ quartus
~
- Error message 1~
Click Start Complication in Processing at the menu bar.~
Start compiling the files, which are created in the proje...
~
''Caution'': A lot of Warning will appear. But, there are...
>
Click Pin Planner in Assignments section. Then, make sure...
~
- Error message 2~
Click Programmer in Tools section at the menu bar. Progra...
~
If the screen indicates No Hardware, click Hardware Setti...
~
''Caution'': If the choice of USB-Blaster is not be displ...
>
As all process has been completed. Click Start, which is ...
As progress reaches at 100% (successful), LED0 on DE0-Nan...
~
#ref(quartus003.png,,60%);~
~
#ref(quickstart.JPG,,20%);~
This is the end of operation check on quickstart.~
* Revision History [#j745fcc1]
>
- 2014/12/25 This article is initially uploaded~
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