- The added line is THIS COLOR.
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[[DE0-Nano/Synthesijer_Samples_Serial1]]
[[labs.beatcraft.com]]~
[[DE0-Nano]]~
[[Synthesijer]]~
[[DE0-Nano/Synthesijer]]~
[[DE0-Nano/Synthesijer_Samples_Serial1]]~
#Contents
*DE0-Nano/Synthesijer_Samples_Serial2 [#o71172b4]
>
This article explains how to build one set of synthesijer_samples, serial_echo on the environment, which has been created at the section of [[DE0-Nano/Synthesijer]]. It shows that this sample, serial_echo is executed on DE0-Nano board.~
~
serial_echo is a sample set, which contains two samples. One sample is called EchoTest, which returns just typed letters. The other sample is ToUpper, which returns typed letters in upper case. This article deals with EchoTest.~
~
As explained in the article of DE0-Nano/Synthesijer_Samples_Serial1, DE0-Nano does not have a serial port, TX and TR are allocated to GPIO PINs. To connect to GPIO, a USB-to-UART cable, C232HD-DDHSP-0 is used. C232HD-DDHSP-0 is a product of FTDI Ltd and equipped with FT232H.~
~
The host PC's serial connection to DE0-Nano is checked by Teraterm.~
(This article do not explain the installation process of the driver for C232HD-DDHSP-0 and Teraterm. Please follow the instructions of these products.)~
This article explains how to build one set of synthesijer_samples, serial_echo on the environment, which has been created at the section of DE0-Nano/Synthesijer. It shows that this sample, serial_echo is executed on DE0-Nano board.
** Modify the source files. [#nc98fab7]
>
The following source files of serial_echo are modified. These modifications are strictly for DE0-Nano and do NOT work with other boards.~
~
Makefile is altered as it is shown below. The target FPGA is DE0-Nano.~
$ vi Makefile
VERILOG_SOURCES = $(SOURCES:.java=.v)
all: hdl exstick
# all: hdl exstick microboard
hdl: $(SOURCES)
serial_echo is a sample set, which contains two samples. One sample is called EchoTest, which returns just typed letters. The other sample is ToUpper, which returns typed letters in upper case. This article deals with EchoTest.
>
The frequency of sys_clk, which is denoted in EchoTest,java, is set to 50MHz.~
$ vi EchoTest.java
public class EchoTest{
private final RS232C_RX_Wrapper rx = new RS232C_RX_Wrapper("sys_clk", "50000000", "rate", "9600");
//private final RS232C_RX_Wrapper rx = new RS232C_RX_Wrapper("sys_clk", "100000000", "rate", "9600");
private final RS232C_TX_Wrapper tx = new RS232C_TX_Wrapper("sys_clk", "50000000", "rate", "9600");
//private final RS232C_TX_Wrapper tx = new RS232C_TX_Wrapper("sys_clk", "100000000", "rate", "9600");
public void run
As explained in the article of DE0-Nano/Synthesijer_Samples_Serial1, DE0-Nano does not have a serial port, TX and TR are allocated to GPIO PINs. To connect to GPIO, a USB-to-UART cable, C232HD-DDHSP-0 is used. C232HD-DDHSP-0 is a product of FTDI Ltd and equipped with FT232H.
>
After the modification is completed, execute make.~
''Caution'': If you already executed the make command, such as you did make for ToUpper of serial_echo, please do make clean. Then, execute make, again.~
~
$ make
The host PC's serial connection to DE0-Nano is checked by Teraterm.
(This article do not explain the installation process of the driver for C232HD-DDHSP-0 and Teraterm. Please follow the instructions of these products.)
>
Then, create a project file for serial_echo by DE0-Nano. The name of the project file is EchoTestTop, which is identical to EchoTestTop of Synthesijer.~
~
Move the created project to Ubuntu. Copy clk_div.vhd, rs232c_rv.vhd, and top.vhd of serial_echo to the same directory as EchoTest.vhd and top.vhd are located. EchoTest.vhd and top.vhd are generated as make is completed.~
~
On Ubuntu, edit EchoTestTop.qsf to match top.vhd, which is just built. To change TOP_LEVEL_ENTITY to top, GPIO[32] and GPIO[33] are allocated to RX and TX, respectively.~
~
$ vi EchoTestTop.qsf
set_global_assignment -name TOP_LEVEL_ENTITY "top"
#set_global_assignment -name TOP_LEVEL_ENTITY "EchoTestTop"
...<Skip>
#============================================================
# CLOCK
#============================================================
set_location_assignment PIN_R8 -to clk
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk
#set_location_assignment PIN_R8 -to CLOCK_50
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50
...<Skip>
set_location_assignment PIN_D12 -to rx_din
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to rx_din
set_location_assignment PIN_B12 -to tx_dout
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to tx_dout
#set_location_assignment PIN_D12 -to GPIO[32]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32]
#set_location_assignment PIN_B12 -to GPIO[33]
#set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33]
#============================================================
# End of pin assignments by Terasic System Builder
#============================================================
set_global_assignment -name VHDL_FILE clk_div.vhd
set_global_assignment -name VHDL_FILE rs232c_rx.vhd
set_global_assignment -name VHDL_FILE rs232c_tx.vhd
set_global_assignment -name VHDL_FILE EchoTest.vhd
set_global_assignment -name VHDL_FILE top.vhd
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
- Modify the source files.
>
GPIO[32] and GPIO[33] on DE0-Nano are connect to the orange lead and yellow lead of C232HD-DDHSP-0, respectively. The black lead, which works as GND, is connected to #12pin, which is located between GPIO[07] and GPIO[09].~
~
''Caution'': Working with C232HD-DDHSP-0, please attach its USB to the host PC.~
~
Next, execute Complication on Quartus, check the allocation of PINs by Pin Planner, and write the build image to DE0-Nano by using Programmer. The details of this process are written in DE0-Nano/Synthesijer_QuickStart.~
~
To check the operation, check the connection of C232HD-DDHSP-0, open up Teraterm ib Windows, and set COM Port at baud rate 9600. As type up any letter, the same letter is repeated like a echo in Teraterm.~
#ref(echotest.png,,50%); ~
>
This is the end of the operation checking of EchoTest of serial_echo~
The following source files of serial_echo are modified. These modifications are strictly for DE0-Nano and do NOT work with other boards.
* Revision History [#c6c9eb4c]
>- 2014/12/25 This article is initially uploaded
Makefile is altered as it is shown below. The target FPGA is DE0-Nano.
<Code>
The frequency of sys_clk, which is denoted in EchoTest,java, is set to 50MHz.
<Code>
After the modification is completed, execute make.
Caution: If you already executed the make command, such as you did make for ToUpper of serial_echo, please do make clean. Then, execute make, again.
<Code $ make>
Then, create a project file for serial_echo by DE0-Nano. The name of the project file is EchoTestTop, which is identical to EchoTestTop of Synthesijer.
Move the created project to Ubuntu. Copy clk_div.vhd, rs232c_rv.vhd, and top.vhd of serial_echo to the same directory as EchoTest.vhd and top.vhd are located. EchoTest.vhd and top.vhd are generated as make is completed.
On Ubuntu, edit EchoTestTop.qsf to match top.vhd, which is just built. To change TOP_LEVEL_ENTITY to top, GPIO[32] and GPIO[33] are allocated to RX and TX, respectively.
<Code>
GPIO[32] and GPIO[33] on DE0-Nano are connect to the orange lead and yellow lead of C232HD-DDHSP-0, respectively. The black lead, which works as GND, is connected to #12pin, which is located between GPIO[07] and GPIO[09].
Caution: Working with C232HD-DDHSP-0, please attach its USB to the host PC.
Next, execute Complication on Quartus, check the allocation of PINs by Pin Planner, and write the build image to DE0-Nano by using Programmer. The details of this process are written in DE0-Nano/Synthesijer_QuickStart.
To check the operation, check the connection of C232HD-DDHSP-0, open up Teraterm ib Windows, and set COM Port at baud rate 9600. As type up any letter, the same letter is repeated like a echo in Teraterm.
This is the end of the operation checking of EchoTest of serial_echo
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