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Synthesijer is a high-level synthesis language, which generates VHDL and Verilong HDL code form Java code, and this is the successor of JavaRock. The articles listed below show how to generate image, how to write the image to a FPGA board, and how to run the images of these samples on a FPGA board.
DE0-Nano is a FPGA board of Terasic Technologies Inc. This board is used for the quick start as well as other samples.
This article explains the set-up for Synthesijer. A virtual machine is installed on a Windows PC, and the most synthesijer related operations are done on this virtual machine.
In the environment that created at DE0-Nano/Synthesijer, create quickstart of sythesijer_samples. Then, execute the created image of the sample on DE0-Nano.
For its details, please visit DE0-Nano/Synthesijer.
In the environment that created at DE0-Nano/Synthesijer, create few programs of sythesijer_samples. Then, execute the creted images of the samples on DE0-Nano.
