![[PukiWiki]](image/bc_logo.png "[PukiWiki]"){kind=logo}
DE0-Nano/Synthesijer_Samples_Serial1
This article explains how to build one set of synthesijer_samples, serial_echo on the environment, which has been created at the section of DE0-Nano/Synthesijer. It shows that this sample, serial_echo is executed on DE0-Nano board.
serial_echo is a sample set, which contains two samples. One sample is called EchoTest, which returns just typed letters. The other sample is ToUpper, which returns typed letters in upper case. This article deals with EchoTest.
As explained in the article of DE0-Nano/Synthesijer_Samples_Serial1, DE0-Nano does not have a serial port, TX and TR are allocated to GPIO PINs. To connect to GPIO, a USB-to-UART cable, C232HD-DDHSP-0 is used. C232HD-DDHSP-0 is a product of FTDI Ltd and equipped with FT232H.
The host PC's serial connection to DE0-Nano is checked by Teraterm. (This article do not explain the installation process of the driver for C232HD-DDHSP-0 and Teraterm. Please follow the instructions of these products.)
The following source files of serial_echo are modified. These modifications are strictly for DE0-Nano and do NOT work with other boards.
Makefile is altered as it is shown below. The target FPGA is DE0-Nano.
Code>
The frequency of sys_clk, which is denoted in EchoTest,java, is set to 50MHz.
Code>
After the modification is completed, execute make. Caution: If you already executed the make command, such as you did make for ToUpper of serial_echo, please do make clean. Then, execute make, again.
Code $ make>
Then, create a project file for serial_echo by DE0-Nano. The name of the project file is EchoTestTop, which is identical to EchoTestTop of Synthesijer.
Move the created project to Ubuntu. Copy clk_div.vhd, rs232c_rv.vhd, and top.vhd of serial_echo to the same directory as EchoTest.vhd and top.vhd are located. EchoTest.vhd and top.vhd are generated as make is completed.
On Ubuntu, edit EchoTestTop.qsf to match top.vhd, which is just built. To change TOP_LEVEL_ENTITY to top, GPIO[32] and GPIO[33] are allocated to RX and TX, respectively.
Code> GPIO[32] and GPIO[33] on DE0-Nano are connect to the orange lead and yellow lead of C232HD-DDHSP-0, respectively. The black lead, which works as GND, is connected to #12pin, which is located between GPIO[07] and GPIO[09].
Caution: Working with C232HD-DDHSP-0, please attach its USB to the host PC.
Next, execute Complication on Quartus, check the allocation of PINs by Pin Planner, and write the build image to DE0-Nano by using Programmer. The details of this process are written in DE0-Nano/Synthesijer_QuickStart.
To check the operation, check the connection of C232HD-DDHSP-0, open up Teraterm ib Windows, and set COM Port at baud rate 9600. As type up any letter, the same letter is repeated like a echo in Teraterm.
This is the end of the operation checking of EchoTest of serial_echo
